1. Field of the Invention
This invention relates to digital integrated circuits and, more particularly, to the reduction of voltage oscillations on the output leads.
2. Description of the Related Art
Integrated circuit (IC) chips are manufactured from semiconducting material, such as silicon or gallium arsenide. The manufacturing process starts with a slice, or wafer, of the semiconducting material. The semiconducting material goes through several process steps to fabricate millions of electrical circuits on the surface of the wafer. These circuits may be grouped and duplicated many times on the wafer. The wafer is then cut into individual groups of circuits called die. The electrical circuits are created with microscopic geometric structures which may be easily damaged if not protected. In many cases, a single die is housed in an enclosure, referred to as a package, which is designed to provide some level of protection to the circuits on the die. Although there are many types of packages, most all packages provide both physical protection and electrical connections from the exterior of the package to the electrical circuits on the surface of the semicondcutor.
There are several methods currently in use to make the electrical connections from the package to the die surface. A common method uses bonding wires. The wires are typically made from aluminum or gold. Referring to FIG. 1, one particular packaging method using a lead frame is shown. The package 30 has several external connections referred to as leads 35 or pins. Together, all of the leads form a structure internal to the package 30 known as a lead frame 40. A die 10 has several bonding areas called pads 20. At the internal end of each lead in the lead frame, there is another bonding area. The bonding areas are used to bond the bonding wires 45.
In many packaging solutions, wire bonding is the common method for making the die to lead frame connections. However, as shown in the complimentary metal oxide semiconductor (CMOS) output driver circuit 50 of FIG. 2, the bond wires have a parasitic inductance 70 per unit length between the package lead 75 and the die pad 80. There is also inductance associated with power 85 and ground 90 connections on the die.
Turning now to FIG. 2, a typical CMOS output driver is shown, including the parasitic inductances described above. When a logic value of zero is applied to input 60, P-channel transistor 51 conducts, acting like a closed switch, thus providing a path for current to flow from Vdd to the package lead. N-channel transistor 52 simultaneously stops conducting, thus acting like an open switch. This effectively drives a logic value of one on the package lead. When a logic value of one is applied to input 60, P-channel transistor 51 opens and N-channel transistor 52 closes, thus providing a path for current to flow from the package lead to circuit ground. This effectively drives a logic value of zero on the package lead. The current that flows each time an opposite logic value is applied is referred to as total switching current 99 and 94, respectively.
The inductances mentioned above can be problematic in that they may cause voltage spikes and oscillations proportional to the magnitude of the total switching current 99 or 94 that flows through the inductance. This is shown by the equation, V=L di/dt. In FIG. 3, the output voltage of CMOS output driver 50 is plotted on the vertical axis and time is plotted on the horizontal axis. The oscillation problem is shown as the logic level switches from a logic one to a logic zero. The voltage oscillating or ringing around zero volts immediately following the voltage transition causes ground bounce 100. A similar condition occurs as a result of a transition from a logic zero to a logic one. The ringing around the Vdd voltage level causes a voltage sag. Although the description of FIG. 1 above is an example of a particular packaging method, it is noted that digital ICs using other packaging methods, such as Ball Grid Array (BGA) packages, may exhibit voltage ringing problems.
In the past, package improvements were made to reduce the package related parasitic inductances. However, as signal frequencies increase, the amount of inductance remaining in improved package designs and the power and ground connection inductance is still problematic. Further package improvements can be costly. Therefore, it is desirable to reduce the effects associated with the parasitic inductance present in packages and power and ground connections without adding additional package costs to a design.